rockchip: clk: rk3128: fix DCLK_VOP_DIV_CON_MASK

The DCLK_VOP_DIV_CON_MASK should cover only bits 8 through 15.
Fix this to remove an "integer-overflow on shifted constant" warning.

Fixes: 9246d9e ("rockchip: rk3128: add clock driver")
Signed-off-by: Philipp Tomsich <[email protected]>

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h
index 3d8317ed91b858701acf6e149e6544ca199db547..90012c7fce0521ecb8dabd33712ca5b9f6793f6d 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3128.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3128.h
@@ -187,7 +187,7 @@ enum {
        DCLK_VOP_SEL_MASK          = 1 << DCLK_VOP_SEL_SHIFT,
        DCLK_VOP_PLL_SEL_CPLL           = 0,
        DCLK_VOP_DIV_CON_SHIFT          = 8,
-       DCLK_VOP_DIV_CON_MASK           = 0xfff << DCLK_VOP_DIV_CON_SHIFT,
+       DCLK_VOP_DIV_CON_MASK           = 0xff << DCLK_VOP_DIV_CON_SHIFT,
 
        /* CRU_CLKSEL31_CON */
        VIO0_PLL_SHIFT          = 5,